(1) Field of the Invention
It is a general object of the present invention to provide a new and improved method of forming an integrated circuit in which special copper interconnects are formed by a combination of physical vapor deposition (PVD) and electrochemical copper deposition (ECD) techniques. By said techniques, high aspect ratio vias and trenches can be filled with copper which is electromigration resistant since interconnects are chemical mechanical polished (CMP) back without dishing effects yielding full cross-sectional lines.
As a background to the current invention, the requirement of lower resistance material has been more stringent as the device dimensions approach micron and sub-micron design ground rules. Pure copper metal lines have been one of the best choices because of copper""s low resistivity and high conductivity. This invention describes the formation of copper films by using a combination of physical vapor deposition (PVD) and electrochemical copper deposition (ECD) techniques. By said techniques, high aspect ratio vias and trenches can be filled with copper without the problem of dishing.
(2) Description of Related Art
The present invention is a new and improved method for fabricating special copper films by using a combination of physical vapor deposition (PVD) and electrochemical copper deposition (ECD) techniques. By said techniques, high aspect ratio vias and trenches can be filled with copper. High conductivity, low resistivity conducting metal lines are important in fabricating quarter micron and below semiconductor devices. The related Prior Art background patents will now be described in this section. These related Prior Art patents are presented with the most recent art described first.
U.S. Pat. No. 5,891,804 entitled xe2x80x9cProcess for Conductors with Selective Depositionxe2x80x9d granted Apr. 6, 1999 to Havermann and Stoltz describes a selective copper deposition using various initiator metals. A method of forming a conductor on an interlevel dielectric layer which is over an electronic microcircuit substrate is described. The method utilizes: forming an intralevel dielectric layer over the interlevel dielectric layer; forming a conductor groove in the intralevel dielectric layer exposing a portion of the interlevel dielectric layer; anisotropically depositing a selective deposition initiator onto the intralevel dielectric layer and onto the exposed portion of the interlevel dielectric layer; and selectively depositing conductor metal to fill the groove to at least half-full. The selective deposition initiator may selected from the group consisting of tungsten, titanium, palladium, platinum, copper, aluminum, and combinations thereof. In one embodiment, the selective deposition initiator is palladium, and the selectively deposited conductor metal is principally copper.
U.S. Pat. No. 5,824,599 entitled xe2x80x9cProtected Encapsulation of Catalytic Layer for Electroless Copper Interconnectxe2x80x9d granted Oct. 20, 1998 to Schacham-Diamand et al shows a selective electroless deposition for a copper interconnect. Once a via or a trench is formed in a dielectric layer, a titanium nitride (TiN) or tantalum (Ta) barrier layer is deposited. Then, a catalytic copper seed layer is conformally blanket deposited in vacuum over the barrier layer. Next, without breaking the vacuum, an aluminum protective layer is deposited onto the catalytic layer to encapsulate and protect the catalytic layer from oxidizing. An electroless deposition technique is then used to auto-catalytically deposit copper on the catalytic layer. The electroless deposition solution dissolves the overlying protective layer to expose the surface of the underlying catalytic layer. The electroless copper deposition occurs on this catalytic surface, and continues until the via/trench is filled. Subsequently, the copper and barrier material are polished by an application of chemical-mechanical polishing (CMP) to remove excess copper and barrier material from the surface, so that the only copper and barrier material remaining are in the via/trench openings. Then an overlying silicon nitride (SiN) layer is formed above the exposed copper in order to form a dielectric barrier layer. The copper interconnect is fully encapsulated from the adjacent material by the TiN (or Ta) barrier layer and the overlying SiN layer.
U.S. Pat. No. 5,789,320 entitled xe2x80x9cPlating of Noble Metal Electrodes for DRAM and FRAMxe2x80x9d granted Aug. 4, 1998 to Andricacos et al describes a noble metal plating process on a preexisting seed layer which is used in the fabrication of electrodes for DRAM and FRAM. The plating may be spatially selective or nonselective. In the nonselective case, a blanket film is first plated and then patterned after deposition by spatially selective material removal. In the selective ease, the plated deposits are either selectively grown in lithographically defined areas by a through-mask plating technique, or selectively grown as a conformal coating on the exposed regions of a preexisting electrode structure. A diamond-like carbon mask can be used in the plating process. A self-aligned process is disclosed for selectively coating insulators in a through-mask process.
U.S. Pat. No. 5,429,987 entitled Method of Profile Control of Selective Metallizationxe2x80x9d granted Jul. 4, 1995 to Allen describes a selective copper deposition for forming interconnects. The method comprises: (a) depositing a selective nucleating layer on the dielectric layer; (b) depositing a sacrificial layer over the nucleating layer; (c) pattering the sacrificial layer and nucleating layer such that the resulting pattern of the nucleating layer and sacrificial layer is equivalent to the desired pattern of conductive lines (d) depositing a sidewall guide material over the patterned sacrificial and nucleating layers; (e) forming sidewall guides; (f) removing the sacrificial layer; and (g) depositing conductive material between the sidewall guides and on the nucleating layer. The nucleating layer may comprise titanium nitride, the sacrificial layer may comprise silicon dioxide, the sidewall guide material may comprise silicon nitride, and the conductive material may comprise copper. In another aspect of the invention, a layer of silicon nitride may be provided over the conductive material.
U.S. Pat. No. 5,112,448 entitled xe2x80x9cSelf-Aligned Process for Fabrication of Interconnect Structures in Semiconductor Applicationsxe2x80x9d granted May 12, 1992 Chakravorty shows a seed layer deposition over polyimide steps. These polyimide steps are utilized to break electrical connection of the seed layer, so that electroplating of copper occurs only in the trenches. The method of fabricating conductors in dielectric trenches is performed in self-aligned manner. Interconnect modules with a high conductor density are achieved by using a copper-polyimide system as a versatile packaging approach. A photosensitive polyimide is applied to a substrate and lithographically patterned to form polyimide steps having a characteristic positive slope, between which are defined trenches in which the substrate is exposed. A thin electroplating seed layer is deposited over the polyimide steps and the substrate. Copper is electroplated into trenches, but does not plate onto the tops of the polyimide steps, since the electroplating seed layer at that location is not electrically connected to the electroplating seed layer in the bottom of the trenches. The electroplating seed layer on top of the polyimide steps is then removed by chemical etching, plasma machining, or ion-milling. A planar structure is eventually obtained without the use of multiple coatings of polyimide layers or any additional masking layers or lift-off layers.
U.S. Pat. No. 4,866,008 entitled xe2x80x9cMethod for Forming Self-Aligned Conductive Pillars on Interconnectsxe2x80x9d granted Sep. 12, 1989 to Brighton and Roane describes a via plug on an metal interconnect using a photoresist mask. Disclosed are methods of forming a self-aligned conductive pillar on an interconnect on a body having semi-conducting surfaces. A first mask defines an inverse pattern for formation of an interconnect. The interconnect is formed by additive metallization processes. A second mask is formed over portions of the first mask and the interconnect. Sidewalls of the first mask which define at least one side of side of said interconnect serve to also define at least one side of said conductive pillar. The second mask also defines at least one side of the conductive pillar. The conductive pillar is formed by additive metal deposition processes. The conductive pillar or metal via plug (W plugs) is thus self-aligned to the interconnect on which it is formed. A cladding layer of tungsten can be used on the multiple layers of seed layer, e.g., molybdenum coated with thin copper, of copper interconnects, and of conductive pillars. Feed layer of nickel and gold interconnect are also disclosed.
The present invention is directed to a novel and improved method of fabrication an integrated circuit, in which special copper films are formed in a dual damascene process, by a combination of physical vapor deposition (PVD), chemical mechanical polish (CMP), and electrochemical copper deposition (ECD) techniques. The methods of the present invention make efficient use of several process steps resulting in less processing time, lower costs and higher device reliability. By said techniques, high aspect ratio vias and trenches can be filled with copper without the problem of dishing.
It is a general object of the present invention to provide a new and improved method of forming an integrated circuit in which special copper films are formed by a combination of physical vapor deposition (PVD) and electrochemical copper deposition (ECD). By said techniques, high aspect ratio trenches can be selectively filled with copper, which are electromigration resistant since the robust interconnects are formed without chemical mechanical polish (CMP) dishing effects.
As a background to the current invention, the requirement of lower resistance material has been more stringent as the device dimensions approach micron and sub-micron design ground rules. Pure copper metal lines have been one of the best choices because of copper""s low resistivity and high conductivity. This invention describes the formation of copper films by using a combination of physical vapor deposition (PVD), selective chemical mechanical polish (CMP) and electrochemical copper deposition (ECD) techniques. By said techniques, high aspect ratio trenches can be filled with robust copper metal without the problem of dishing.
As a background to the present invention, provided by Prior Art methods are the following: a semiconductor silicon substrate with the first level of metal copper wiring being defined, on the first layer of insulator, silicon oxide SiOx. The invention starts with these conventional layers being provided by Prior Art methods, in addition, to patterned and etched trenches, being defined in deposited insulating material.
The starting point of this invention is the conformal blanket deposition of a met al diffusion barrier layer, beneath subsequent metal copper wiring layers. To obtain adequate diffusion barrier liner coverage, collimated reactive sputtered, physical vapor deposition (PVD) of TaN, Ti/TiN, TiN, WN liners, which form metal copper diffusion barriers and adhesion aids, is utilized. The conformal liner lines the trench.
Next in the process is the blanket deposition of a copper seed layer by physical vapor deposition (PVD) or sputtering. Note, the conformal film lines the trench.
The next process step is the first embodiment of this invention. It is the selective polishing back of the seed layer over the insulator by a special chemical mechanical polishing step (CMP), whereby the seed layer remains in the trench and only the seed layer that is over the insulator is removed. Note, this process step is performed in such a way, as to leave the blanket diffusion barrier layer in place over the insulator.
The next process step is yet another embodiment of this invention. A special, selective electrochemical deposition (ECD) of copper metal is performed, with deposition taking place only on the seed layer, which is in the trench. This auto-plating or xe2x80x9cplate-upxe2x80x9d occurs exclusively in the trench. This process provides good sealing around the trench perimeter and fine copper metal coverage of the trench for subsequent robust interconnects. The selective plating of copper provides a copper film that is easily removed by subsequent chemical mechanical polish (CMP) and tends to more uniform and free of the usual defects associated with CMP films.
In the final embodiments of this invention, the remaining process steps are: a special chemical mechanical polish (CMP) of excess conducting metal, in a manner to form conducting lines without deleterious dishing effects. Also, the remaining diffusion barrier material is removed from the surface where it covered the surface of the insulator.
In summary, the damascene method described by this invention utilizes a selective copper electrochemical deposition (ECD) to improve the copper metal gap-fill performance. In addition, using selective growth yields positive effects on the damascene structure, i.e., improved sealing around the damascene structure and enhanced electromigration (EM) performance of the copper. Finally, using selective copper growth reduces the non-uniformities, characteristic of the metal film during the subsequent chemical mechanical polish (CMP) process and minimizes deleterious dishing effects.
This invention has been summarized above and described with reference to the preferred embodiments. Some processing details have been omitted and are understood by those skilled in the art. More details of this invention are stated in the xe2x80x9cDESCRIPTION OF THE PREFERRED EMBODIMENTSxe2x80x9d section.